Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors, or 6 transistors, which result in much lower density, with typical cell size being between about 60 F2 and 150 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in providing a bi-stable element for such memory cells and in overcoming many previously unresolved problems for thyristor-based memory applications. This type of NDR device has a control port that is capacitively coupled to a relatively-thin thyristor body. The thyristor body is sufficiently thin to permit modulation of the potential of the thyristor body in response to selected signals capacitively coupled via the control port. Such capacitively-coupled signals are used to enhance switching of the thyristor-based device between current-blocking and current-conducting states.
An important consideration in the design of thyristor-based memory cells, including the above thyristor-based type, concerns maintenance of the thyristor's conducting state. When the thyristor is in the forward conducting state, a DC current larger than the holding current of the thyristor flows through the thyristor in order to maintain the conducting state. For the specific case of the above thyristor-based type memory cell, optimal operation of the device is challenged by various issues. For example, when a MOSFET access transistor is used to control the current flow through a thyristor, variations in the threshold voltage of access transistors from cell to cell in a large array and the exponential current-voltage dependence for access transistors in the sub-threshold regime can result in an unduly large standby current for the array and/or loss of the conducting state for some of the thyristors in the array. In addition, unduly large standby resistors often can be used in each memory cell. This resistor can add to the bit-cost of the memory by adding some extra steps to the fabrication process and potentially increasing the memory cell size. Furthermore, the resistance variation of the standby resistor used from cell to cell can result in a large standby current for the array and/or loss of the conducting state for some of the thyristors in the array. Other related challenges include variations in bit-line voltage during read and write operations into one cell and a resultant large standby current and/or loss of the conducting state for the other cells sharing the same bit line.